Scaling of semiconductor devices (e.g., a metal-oxide semiconductor field-effect transistor) has enabled continued improvement in speed, performance, density, and cost per unit function of integrated circuits over the past few decades. In accordance with a design of the transistor and one of the inherent characteristics thereof, modulating a length of a channel region underlying a gate between a source and drain of the transistor alters a resistance associated with the channel region, thereby affecting a performance of the transistor. More specifically, shortening the length of the channel region reduces a source-to-drain resistance of the transistor, which, assuming other parameters are maintained relatively constant, may allow an increase in current flow between the source and drain when a sufficient voltage is applied to the gate of the transistor.
Continued scaling of MOS devices results in severe degradation of carrier mobility, however, which in turn adversely affects the device drive current. To further enhance the performance of MOS devices, carrier mobility enhancement becomes a key element in developing next generation technologies. Among efforts to improve carrier mobility, introducing stress into the channel region of MOS devices is widely adopted. Generally, it is desirable to induce a tensile stress in the channel region of an n-type metal-oxide-semiconductor (“NMOS”) device in a source-to-drain direction and to induce a compressive stress in the channel region of a p-type metal-oxide-semiconductor (“PMOS”) device in a source-to-drain direction.
A commonly used method for applying compressive stress to the channel regions of PMOS devices is growing SiGe stressors in source and drain regions of the respective PMOS devices. Such a method typically includes the steps of forming recesses in a silicon substrate along edges of gate spacers, epitaxially growing SiGe stressors in the recesses, and annealing. Since SiGe has a greater lattice constant than does the silicon substrate, after annealing, it expands and applies a compressive stress to the channel region, which is located between a source SiGe stressor and a drain SiGe stressor.
The above-discussed method, however, suffers drawbacks when used for the formation of static random access memory (SRAM) cells. FIG. 1 illustrates an exemplary circuit diagram of a six-transistor SRAM cell, which includes pass-gate transistors 10 and 24, pull-up transistors 12 and 16, and pull-down transistors 14 and 18. Gate 2 of the pass-gate transistor 10 is controlled by a word-line WL that determines whether the current SRAM cell is selected or not. A latch formed of pull-up transistors 12 and 16 and pull-down transistors 14 and 18 stores a state. The stored state can be read through a bit line BL.
Conventionally, on a memory chip, PMOS devices in both core circuits and memory circuits are formed with SiGe stressors. However, with greater device drive currents for pull-up transistors 12 and 16, although read operations are improved, write margins of the SRAM cells are degraded. For high performance SRAM cells, read and write operations are preferably balanced. Therefore, it is preferred that drive currents of pull-up devices in SRAM cells be controlled.
Logically, a possible solution for such a problem is to form SiGe stressors for PMOS devices in the core circuit, but not for the pull-up PMOS devices in SRAM cells. However, since the core circuit typically occupies a small region on a memory chip, SiGe stressors will only be formed in the small region, resulting in pattern loading effects and process difficulties for subsequent process steps. This solution is thus not preferred.
What is needed in the art, therefore, is a method for forming SRAM cells that may incorporate SiGe stressors to take advantage of the benefits associated with the compressive stress while at the same time overcoming the deficiencies of the prior art.